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this is information on a product in full production. july 2014 docid023889 rev 3 1/15 15 STL130N8F7 n-channel 80 v, 3 m ? , 130 a stripfet? f7 power mosfet in a powerflat? 5x6 package datasheet - production data figure 1. internal schematic diagram features ? ultra low on-resistance ? 100% avalanche tested applications ? switching applications description this n-channel power mosfet utilizes stripfet? f7 technology with an enhanced trench gate structure that results in very low on- state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. 1 2 3 4 powerflat? 5x6 $0y ' * 6 order code v ds r ds(on) max i d p tot STL130N8F7 80 v 3.6 m ? (v gs =10 v) 130 a 135 w table 1. device summary order code marking package packaging STL130N8F7 130n8f7 powerflat? 5x6 tape and reel www.st.com
contents STL130N8F7 2/15 docid023889 rev 3 contents 1 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
docid023889 rev 3 3/15 STL130N8F7 electrical ratings 1 electrical ratings table 2. absolute maximum ratings symbol parameter value unit v ds drain-source voltage 80 v v gs gate-source voltage 20 i d (1) 1. this value is rated according to r thj-c . drain current (continuous) at t c = 25 c 130 a i d (1) drain current (continuous) at t c = 100 c 93 i d (2) 2. this value is rated according to r thj-pcb . drain current (continuous) at t pcb = 25 c 26 i d (2) drain current (continuous) at t pcb = 100 c 19 i dm (1)(3) 3. pulse width is limited by safe operating area. drain current (pulsed) 560 i dm (2)(3) drain current (pulsed) 104 p tot (1) total dissipation at t c = 25 c 135 w p tot (2) total dissipation at t pcb = 25 c 4.8 w e as (4) 4. starting t j =25c, i d =18.5 a, v dd =50 v single pulse avalanche energy 515 mj t j t stg operating junction temperature storage temperature -55 to 175 c table 3. thermal data symbol parameter value unit r thj-pcb (1) 1. when mounted on fr-4 board of 1inch2, 2oz cu, t < 10 sec. thermal resistance junction-pcb 31.3 c/w r thj-case thermal resistance junction-case 1.1 c/w
electrical characteristics STL130N8F7 4/15 docid023889 rev 3 2 electrical characteristics (t j = 25 c unless otherwise specified) table 4. on/off states symbol parameter test conditions min typ max unit v (br)dss drain-source breakdown voltage v gs = 0, i d = 250 a 80 v i dss zero gate voltage drain current v gs = 0, v ds = 80 v 1 a v gs = 0, v ds = 80 v, t j = 125 c 10 a i gss gate body leakage current v ds = 0, v gs = 20 v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 2.5 4.5 v r ds(on) static drain-source on-resistance v gs = 10 v, i d = 13 a 3 3.6 m ? table 5. dynamic symbol parameter test conditions min typ max unit c iss input capacitance v gs =0, v ds = 40 v, f=1 mhz - 6340 - pf c oss output capacitance - 1195 - pf c rss reverse transfer capacitance -105 - pf q g total gate charge v dd =40 v, i d = 26 a v gs =10 v -96 - nc q gs gate-source charge - 29 - nc q gd gate-drain charge - 26 - nc table 6. switching times symbol parameter test conditions min typ max unit t d(on) turn-on delay time v dd =40 v, i d = 13 a, r g =4.7 ? , v gs =10 v -26-ns t r rise time - 51 - ns t d(off) turn-off delay time - 82 - ns t f fall time - 44 - ns
docid023889 rev 3 5/15 STL130N8F7 electrical characteristics table 7. source drain diode symbol parameter test conditions min typ max unit i sd source-drain current - 26 a i sdm (1) 1. pulse width is limited by safe operating area. source-drain current (pulsed) - 104 v sd (2) 2. pulse test: pulse duration = 300 s, duty cycle 1.5%. forward on voltage v gs =0, i sd = 26 a - 1.2 v t rr reverse recovery time i sd = 26 a, di/dt = 100 a/s, v dd =60 v, t j 150 c -58 ns q rr reverse recovery charge - 92 nc i rrm reverse recovery current - 3.2 a
electrical characteristics STL130N8F7 6/15 docid023889 rev 3 2.1 electrical characteristics (curves) figure 2. safe operating area figure 3. thermal impedance figure 4. output characteristics figure 5. transfer characteristics figure 6. gate charge vs gate-source voltage figure 7. static drain-source on-resistance i d 100 10 1 0.1 0.1 1 v ds (v) 10 (a) operation in this area is limited by max rds(on) 1s 10ms tj=175c tpcb=25c sinlge pulse 100ms gipd120920131413fsr k t p (s) 10 -1 10 -2 10 -3 10 0 10 -1 10 -2 10 -3 10 -4 pcb 10 1 single pulse 0.05 0.02 0.01 0.1 0.2 =0.5 gipd130920131022fsr i d 60 40 20 0 02 v ds (v) 4 (a) 4v 5v 6v v gs = 10v 68 80 100 120 140 160 gipd120920131428fsr i d 60 40 20 0 0 2 v gs (v) 4 (a) v ds = 2v 68 80 100 120 140 160 1 357 180 gipd120920131444fsr v gs 6 4 2 0 0 40 q g (nc) 80 (v) v dd = 40v i d = 26a 8 10 12 20 60 100 gipd120920131452fsr r ds(on) 3.05 3 2.95 2.90 4 12 i d (a) 20 (m) v gs = 10v 3.10 816 24 gipd120920131501fsr
docid023889 rev 3 7/15 STL130N8F7 electrical characteristics figure 8. capacitance variations figure 9. normalized v (br)dss vs temperature figure 10. normalized gate threshold voltage vs temperature figure 11. normalized on-resistance vs temperature figure 12. source-drain diode forward characteristics c 3000 2000 1000 0 020 v ds (v) 40 (pf) c iss 4000 10 30 50 c oss c rss 60 70 5000 6000 7000 8000 gipd120920131512fsr v (br)dss 1 0.98 0.96 0.94 -75 -25 t j (c) 25 (norm) 1.02 075125 1.04 i d = 250a gipd120920131527fsr v gs(th) 1 0.8 0.6 0.4 -75 -25 t j (c) 25 (norm) 1.2 0 75 125 i d = 250a gipd120920131608fsr r ds(on) 1 0.8 0.6 0.4 -75 -25 t j (c) 25 (norm) 1.2 075125 i d = 13a v gs = 10v 1.4 1.6 1.8 gipd120920131652fsr v ds 0.7 0.6 0.5 0.4 48 i d (a) 16 (v) 0.8 12 20 24 t j = -55c 0.9 t j = 25c t j = 175c gipd130920131009fsr
test circuits STL130N8F7 8/15 docid023889 rev 3 3 test circuits figure 13. switching times test circuit for resistive load figure 14. gate charge test circuit figure 15. test circuit for inductive load switching and diode recovery times figure 16. unclamped inductive load test circuit figure 17. unclamped inductive waveform figure 18. switching time waveform am01468v1 v gs p w v d r g r l d.u.t. 2200 f 3.3 f v dd am01469v1 v dd 47k 1k 47k 2.7k 1k 12v v i =20v=v gmax 2200 f p w i g =const 100 100nf d.u.t. v g am01470v1 a d d.u.t. s b g 25 a a b b r g g fast diode d s l=100 h f 3.3 1000 f v dd am01471v1 v i p w v d i d d.u.t. l 2200 f 3.3 f v dd am01472v1 v (br)dss v dd v dd v d i dm i d am01473v1 v ds t on td on td off t off t f t r 90% 10% 10% 0 0 90% 90% 10% v gs
docid023889 rev 3 9/15 STL130N8F7 package mechanical data 4 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
package mechanical data STL130N8F7 10/15 docid023889 rev 3 figure 19. powerflat? 5x6 type s-c mechanical data b,b& 7rsylhz 6lghylhz %rwwrpylhz 3lq lghqwlilfdwlrq 3lq lghqwlilfdwlrq
docid023889 rev 3 11/15 STL130N8F7 package mechanical data figure 20. powerflat? 5x6 recommended footprint (dimensions in mm) table 8. powerflat? 5x6 type s-c mechanical data dim. mm min. typ. max. a0.80 1.00 a1 0.02 0.05 a2 0.25 b0.30 0.50 d5.20 d2 4.11 4.31 e6.15 e1.27 e1 0.65 e2 3.50 3.70 e3 2.35 2.55 e4 0.40 0.60 e5 0.08 0.28 k1.05 1.35 l 0.715 1.015 footprint
packaging mechanical data STL130N8F7 12/15 docid023889 rev 3 5 packaging mechanical data figure 21. powerflat? 5x6 tape (a) figure 22. powerflat? 5x6 package orientation in carrier tape. a. all dimensions are in millimeters. measured from centerline of sprocket hole to centerline of pocket. cumulative tolerance of 10 sprocket holes is 0.20 . measured from centerline of sprocket hole to centerline of pocket. (i) (ii) (iii) all dimensions are in millimeters 2 2.00.1 (i) bo (5.300.1) ko (1.200.1) 0.05) ?1.5 min. ?1.550.05 p ao(6.300.1) f(5.500.1)(iii) w(12.000.3) 1.750.1 4.00.1 (ii) p 0 y y section y-y c l p1(8.000.1) do d1 e 1 (0.30 t ref.r0.50 ref 0.20 base and bulk quantity 3000 pcs 8234350_tape_rev_c pin 1 identification
docid023889 rev 3 13/15 STL130N8F7 packaging mechanical data figure 23. powerflat? 5x6 reel 2.20 ?21.2 13.00 core detail 2.50 1.90 r0.60 77 128 ?a r1.10 2.50 4.00 r25.00 part no. w1 w2 18.4 (max) w3 06 ps esd logo at t e n t i o n observe precautions for handling electrostatic sensitive devices 11.9/15.4 12.4 (+2/-0) a 330 (+0/-4.0) all dimensions are in millimeters ?n 178(2.0) 8234350_reel_rev_c
revision history STL130N8F7 14/15 docid023889 rev 3 6 revision history table 9. document revision history date revision changes 21-may-2013 1 first release. 23-sep-2013 2 document status promoted form preliminary to production data. inserted section 2.1: electrical characteristics (curves) . 25-jul-2014 3 ? modified: title and description ? modified: i d and p tot values in cover page ? updated: figure 13 , 14 , 15 and 16 ? updated: section 4: package mechanical data ? minor text changes
docid023889 rev 3 15/15 STL130N8F7 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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